Computer-based control systems have been widely used in the automotive industry to control various vehicular functions including those associated with the internal combustion engine, vehicle drivetrain and other vehicle operating systems. A typical automotive control system is microprocessor-based and is often referred to as an engine control module (ECM), powertrain control module (PCM), engine control computer (ECC) or the like.
Automotive control systems of the foregoing type typically manage engine and vehicle operation via software algorithms resident in memory. Such algorithms generally fall into two categories: (1) vehicle operational algorithms, and (2) vehicle diagnostics algorithms. Vehicle operational algorithms are often carried out in accordance with calibration data stored in memory. Vehicle diagnostics algorithms, on the other hand, typically require access to memory for retrieval of known or expected vehicle operational parameters and for storage of diagnostics information relating to vehicle operation.
Automotive control systems of the type described hereinabove must therefore be equipped with sufficient memory for storing at least the operational and diagnostics algorithms, the vehicle calibration data and the vehicle diagnostics information. Such memory typically includes both volatile and non-volatile memory components which may take the form of random access memory (RAM) and any of a variety of read only memories (ROM) such as, for example, UV erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and the like.
In recent years, many automotive control systems have replaced one or more of the foregoing memory units with one or more flash memory units which have desirable properties of both volatile and non-volatile memories. For example, flash memories offer long term reliable storage of data therein, yet permit relatively simple reprogramming thereof, typically in the form of block erasures and writes.
As with many large capacity storage mediums, access to large capacity flash memories can be relatively slow, and access speed can be greatly improved by using a faster memory unit, such as RAM, to temporarily store data resident in flash. During system operation, data is more quickly accessed via RAM, and the RAM contents are typically copied back to flash memory for permanent storage prior to system shut down. In the automotive industry, such a scheme has typically involved the use of a so-called shadow RAM which has a capacity approximately equal to that of the flash memory. In operation, access to data contained within the flash memory is accomplished by accessing a copy of the data via the faster shadow RAM. The modified contents of the shadow RAM are then copied back to the flash memory just prior to shut down of the system.
The shadow RAM approach, while widely used, has several drawbacks associated therewith. For example, flash memory is typically not updated by the contents of the shadow RAM until system shutdown, so that a potentially large amount of data may have been modified by that time. If the correspondingly lengthy flash memory updating procedure is interrupted for some reason, valuable data may be lost. Further, as the need for additional flash memory capacity increases, the capacity of shadow RAM must likewise increase. At some point, the cost of additional shadow RAM, both monetarily and in terms of physical space consumption, cannot be justified.
As an alternative to the shadow RAM approach used in some automotive control systems, it is known in the computer art to use cache memory to speed up the performance of systems having slower access devices. Typically, part of a RAM is used as a cache for temporarily holding the most recently accessed data from the slower storage device. Thus, while the slower storage device may have a large storage capacity, a much smaller RAM, or portion of a RAM, may be used as the data access cache. This scheme works well in situations where the same data is repeatedly operated on, which is often the case with typical software architectures.
While the foregoing caching technique may solve the problem associated with the storage capacity required of the RAM, it has other drawbacks associated therewith. For example, most conventional cache designs are read caches for speeding up reads from the slower access memory device. While write caches have been used, data is typically written to the slower access storage device at the same time it is written to the write cache due to the concern for loss of updated data files in case of power loss. In an automotive engine control system, a flash memory could therefore not be updated during engine operation due to the long write times associated with the updating operation. In such systems, RAM caches are therefore typically not used, and larger RAM devices are required which write data back to flash memory only after engine operation ceases.
As another example, while typical flash memories are addressable on either even or odd boundaries when operating in a byte access mode (8 bit data items), such memories are addressable only on even boundaries when operating in word or long word access modes (16 or 32 bit data items respectively). Thus, in an automotive engine control system operating strictly in a word/long word access mode, operating system commands attempting to access odd flash memory addresses will generate address errors so that processing of such instructions cannot be carried out in accordance with conventional techniques.
In an automotive control system, what is therefore needed is a caching technique operable to move areas of flash memory into and out of a substantially smaller capacity RAM cache, wherein any particular flash area is updated by the modified contents of the RAM cache either periodically or when the cache is reloaded with a new flash area. Since typical flash memories are only addressable on even boundaries during word/long word access modes of operation, such a caching technique should further include provisions for disallowing byte access operation and for modifying odd memory access addresses generated by the operating system operating in word/long word access mode so that such addresses properly map to an appropriate flash address within the cache.